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NB100LVEP17 2.5V / 3.3V Quad Differential Driver/Receiver
Description
The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Inputs of unused gates can be left open and will not affect the operation of the rest of the device.
Features
http://onsemi.com MARKING DIAGRAMS*
N100 VP17 ALYWG G TSSOP-20 DT SUFFIX CASE 948E 24 1
24 1
* * * * * * * * *
Maximum Input Clock Frequency > 2.5 GHz Typical Maximum Input Data Rate > 2.5 Gb/s Typical 250 ps Typical Propagation Delay Low Profile QFN Package PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V Q Output Will Default LOW with Inputs Open or at VEE VBB Output Pb-Free Packages are Available
24 PIN QFN MN SUFFIX CASE 485L A L Y W G
N100 VP17 ALYWG G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 7
1
Publication Order Number: NB100LVEP17/D
NB100LVEP17
D0 R1 D0 R1 D1 R1 D1 R1 D2 R1 D2 R1 D3 R1 D3 R1 Q0 R2 Q0
Q1 R2 Q1
Q2 R2 Q2 VCC VEE Q3 R2 Q3 VBB
Figure 1. Logic Diagram
Table 1. PIN DESCRIPTION
Pin TSSOP 1,20 11 QFN Name VCC VEE VBB D[0:3] D[0:3] Q[0:3] Q[0:3] NC EP I/O - - - ECL Input ECL Input ECL Output ECL Output - - Default State - - - Low High - - -
AAAA A AAAAAAAA AAAAA
13,18,21, 22,23 10 9 1,3,5,7 2,4,6,8 12,15,17,2 0 11,14,16,1 9 24 - 10 2,4,6,8 3,5,7,9 19,17,15,13 18,16,14,12 N/A N/A
Description Positive Supply Voltage. All VCC Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. Negative Supply Voltage. All VEE Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. ECL Reference Voltage Output. Noninverted Differential Inputs [0:3]. Internal 75 kW to VEE. Inverted Differential Inputs [0:3]. Internal 75 kW to VEE and 37 kW to VCC. Noninverted Differential Outputs [0:3]. Typically Terminated with 50 W to VTT = VCC - 2 V. Inverted Differential Outputs [0:3]. Typically Terminated with 50 W to VTT = VCC - 2 V. No Connect. The NC Pin is Electrically Connected to the Die and "MUST BE" Left Open. Exposed Pad. (Note 1)
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally conductive expose pad on the package bottom (see case drawing) must be attached to a heat-sinking conduit.
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NB100LVEP17
NC VCC VCC VCC Q0 24 VCC Q0 20 19 Q0 18 Q1 Q1 17 16 Q2 15 Q2 14 Q3 13 Q3 VEE 12 11 D0 D0 D1 NB100LVEP17 D1 D2 1 VCC 2 D0 3 D0 4 D1 5 D1 6 D2 7 D2 8 D3 9 10 D3 VBB D2 1 2 3 4 5 6 7 D3 8 D3 9 10 11 Q3 12 Q3 NB100LVEP17 23 22 21 20 Q0 19 18 17 16 15 14 13 VCC Q1 Q1 Q2 Q2 VCC Exposed Pad (EP)
VBB VEE
Figure 2. TSSOP-20 Lead Pinout (Top View)
Figure 3. QFN-24 Lead Pinout (Top View)
Table 2. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection (R1) (R2) Human Body Model Machine Model Charged Device Model Pb Pkg Level 1 Level 1 Value 75 kW 37 kW > 2 kV > 150 V > 2 kV Pb-Free Pkg Level 1 Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) TSSOP-20 QFN-24 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in 274 Devices
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NB100LVEP17
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJA Parameter Positive Mode Power Supply Negative Mode Power Supply Positive Mode Input Voltage Negative Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) JEDEC 51-3 (1S - Single Layer Test Board) Thermal Resistance (Junction-to-Ambient) JEDEC 51-6 (2S2P Multilayer Test Board) with Filled Thermal Vias Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm 0 lfpm 500 lfpm Standard Board 20 TSSOP 20 TSSOP 24 QFN 24 QFN 20 TSSOP 24 QFN Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 6 -6 6 -6 50 100 $0.5 -40 to +85 -65 to +150 140 50 37 32 23 to 41 11 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C
qJC Tsol
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 4. DC CHARACTERISTICS, PECL VCC = 2.5 V; VEE = 0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) (Note 4) Input LOW Voltage (Single-Ended) (Note 4) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 5) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) D D 0.5 -150 Min 30 1355 555 1335 555 1.2 Typ 40 1480 775 Max 50 1605 900 1620 875 2.5 150 0.5 -150 Min 30 1355 555 1335 555 1.2 25C Typ 40 1480 775 Max 50 1605 900 1620 875 2.5 150 0.5 -150 Min 30 1355 555 1275 555 1.2 85C Typ 40 1480 775 Max 55 1605 900 1620 875 2.5 150 Unit mA mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary -0.125 V to +1.3 V. 3. All loading with 50 W to VEE = VCC - 2.0 V. 4. Do not use VBB at VCC < 3.0 V. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NB100LVEP17
Table 5. DC CHARACTERISTICS, PECL VCC = 3.3 V; VEE = 0 V (Note 6)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) ECL Output Reference Voltage (Note 8) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) D D 0.5 -150 Min 30 2155 1355 2135 1355 1775 1.2 1875 Typ 40 2280 1575 Max 50 2405 1700 2420 1675 1975 3.3 150 0.5 -150 Min 30 2155 1355 2135 1355 1775 1.2 1875 25C Typ 40 2280 1575 Max 50 2405 1700 2420 1675 1975 3.3 150 0.5 -150 Min 30 2155 1355 2135 1355 1775 1.2 1875 85C Typ 40 2280 1575 Max 55 2405 1700 2420 1675 1975 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.5 V to -0.3 V. 7. All loading with 50 W to VCC - 2.0 V. 8. Single ended input operation is limited VCC 3.0 V in PECL mode. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 6. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -2.375 V to -3.8 V (Note 10)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Negative Power Supply Current Output HIGH Voltage (Note 11) Output LOW Voltage (Note 11) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) ECL Output Reference Voltage (Note 12) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) D D 0.5 -150 Min 30 -1145 -1945 -1165 -1945 -1525 -1425 Typ 40 -1020 -1725 Max 50 -895 -1600 -880 -1600 -1325 0.0 Min 30 -1145 -1945 -1165 -1945 -1525 -1425 25C Typ 40 -1020 -1725 Max 50 -895 -1600 -880 -1600 -1325 0.0 Min 30 -1145 -1945 -1165 -1945 -1525 -1425 85C Typ 40 -1020 -1725 Max 55 -895 -1600 -880 -1600 -1325 0.0 Unit mA mV mV mV mV mV V
VEE + 1.2
VEE + 1.2
VEE + 1.2
IIH IIL
150 0.5 -150
150 0.5 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. 11. All loading with 50 W to VCC - 2.0 V. 12. Single ended input operation is limited VEE -3.0V in NECL mode. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NB100LVEP17
Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = -2.375 V to -3.8 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 14)
-40C Symbol VOUTPP Characteristic Output Voltage Amplitude (See Figures 4, 5) Propagation Delay to Output Differential Pulse Skew (Note 15) Within Device Skew (Note 17) Device-to-Device Skew (Note 17) RMS Random Clock Jitter (Note 18) Peak-to Peak Data Dependent Jitter (Note 19) fin = 2.5 GHz fin = 1.5 Gb/s fin = 2.5 Gb/s 150 Q, Q fin < 1 GHz fin = 2 GHz fin = 2.5 GHz D to Q, Q Min 600 400 300 200 Typ 700 500 400 250 5 5 25 0.5 5 5 800 325 25 25 100 1 15 15 1200 150 Max Min 600 325 250 200 25C Typ 700 500 400 250 5 5 25 0.5 5 5 800 325 25 25 100 1 15 15 1200 150 Max Min 550 300 200 225 85C Typ 700 500 400 300 5 5 25 0.5 5 5 800 350 25 25 100 1 15 15 1200 Max Unit mV
tPLH, tPHL tSkew
ps ps
tJITTER
ps
VINPP tr tf
Input Voltage Swing (Differential Configuration) (Note 20) Output Rise/Fall Times @ 50 MHz (20% - 80%)
mV ps
125
175
225
140
190
240
150
200
250
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. Input edge rates 150 ps (20% - 80%). 15. Pulse Skew = |tPLH - tPHL| 16. Worst case difference between Q0 and Q1 outputs. 17. Skew is measured between outputs under identical transitions. 18. Additive RMS jitter with 50% Duty Cycle Clock Signal at 2.5 GHz. 19. Peak-to-Peak jitter with input NRZ data at PRBS 231-1 at 2.5 Gb/s with all inputs active. 20. Input voltage swing is a single-ended measurement operating in differential mode, with minimum propagation change of 50 ps.
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NB100LVEP17
850 OUTPUT VOLTAGE AMPLITUDE (mV) 750 Q AMP (mV) 650 550 450 350 250 10 9.0 8.0 6.0 5.0 4.0 3.0 2.0 RMS JITTER (ps) 0.5 1.0 1.5 2.0 2.5 1.0 0 RMS JITTER (ps) RMS JITTER (ps) 7.0
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at VCC = 2.5 V, Ambient Temperature
OUTPUT VOLTAGE AMPLITUDE (mV)
850 750 650 550 450 350 250
10 9.0 Q AMP (mV) 8.0 7.0 6.0 5.0 4.0 3.0 2.0 RMS JITTER (ps) 0.5 1.0 1.5 2.0 2.5 1.0 0
INPUT FREQUENCY (GHz)
Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at VCC = 3.3 V, Ambient Temperature
D VINPP = VIH(D) - VIL(D) D Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 6. AC Reference Measurement
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NB100LVEP17
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 7. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device NB100LVEP17DT NB100LVEP17DTG NB100LVEP17DTR2 NB100LVEP17DTR2G NB100LVEP17MN NB100LVEP17MNG NB100LVEP17MNR2 NB100LVEP17MNR2G Package TSSOP-20* TSSOP-20* TSSOP-20* TSSOP-20* QFN-24 QFN-24 (Pb-Free) QFN-24 QFN-24 (Pb-Free) Shipping 75 Units / Rail 75 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 92 Units / Rail 92 Units / Rail 3000 Tape & Reel 3000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *This package is inherently Pb-Free.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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NB100LVEP17
PACKAGE DIMENSIONS
TSSOP-20 CASE 948E-02 ISSUE C
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1 J J1
2X
L/2
20
11
L
PIN 1 IDENT 1 10
B -U- N
SECTION N-N 0.25 (0.010) M
0.15 (0.006) T U
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
A -V-
N F DETAIL E -W-
DIM A B C D F G H J J1 K K1 L M
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
16X
16X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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IIII IIII IIII
0.65 PITCH
DIMENSIONS: MILLIMETERS
NB100LVEP17
PACKAGE DIMENSIONS
QFN 24 MN SUFFIX 24 PIN QFN, 4x4 CASE 485L-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.23 0.28 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.35 0.45
D
PIN 1 IDENTIFICATION
A
B
E
2X
0.15 C
2X
0.15 C A2 0.10 C A
0.08 C
SEATING PLANE
A1 D2 e
12 13
A3
DIM A A1 A2 A3 b D D2 E E2 e L
REF
C
L
7 6
E2
24X
b
1 24 19
18
0.10 C A B 0.05 C
e
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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NB100LVEP17/D

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